A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. In particular, flash memory is a type of electronic memory media that can be rewritten and that can retain content without consumption of power. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors. Flash memory technology can include NOR flash memory and NAND flash memory, for example. NAND flash memory evolved from DRAM technology and NOR flash memory evolved from electrically erasable read only memory (EEPROM) chip technology, in which, unlike flash memory, a single byte can be erased. While NAND flash is typically suitable for sequential access to handle semi-static data storage like pictures, music, etc., NOR flash is typically suitable for random access application such as code storage where execution in place is required (e.g., including set-top box applications, personal computers, cell phones, etc.). However, NAND flash can be used for some boot-up operations as well being combined with other memory types (e.g., DRAM) for execute in place functionality. In addition, flash memory devices typically are less expensive and more dense as compared to many other memory devices, meaning that flash memory devices can store more data per unit area.
Flash memory has become popular, at least in part, because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory is nonvolatile; it can be rewritten and can hold its content without power. It can be used in many portable electronic products, such as cell phones, portable computers, voice recorders, thumbnail drives and the like, as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. The fact that flash memory can be rewritten, as well as its ability to retain data without a power source, small size, and light weight, have all combined to make flash memory devices useful and popular means for transporting and maintaining data.
Although NAND flash memory chips from different vendors often use similar packaging, have similar pinouts, and accept similar sets of low-level commands, subtle differences in timing and/or command set can provide suboptimal performance if the flash controller (e.g., flash channel interface) is not specifically designed and tested for the specific NAND flash implementation. As a result, flash products typically require thorough debugging and testing to incorporate a new and/or different model of flash chip. In addition, multi-vendor flash controllers must typically store a table of supported flash devices in firmware to deal with differences in the flash device interfaces. Accordingly, this can result in increased cost, complexity, and time-to-market of flash based products, in addition to potential incompatibility with future NAND flash releases where required firmware update would otherwise be required. Thus a flash channel interface that can be flexibly and rapidly reprogrammed to accommodate various flash device implementations is desired to reduce cost, complexity, and time to market.
One effort to mitigate such development complexities is the Open NAND Flash Interface Working Group (ONFI). ONFI is a consortium of technology companies working to develop open standards for NAND flash memory chips and devices that communicate with them. ONFI seeks to standardize the low-level interface to raw NAND flash chips, which are the most widely used form of non-volatile memory integrated circuits. As NAND flash becomes more of a commodity product, one main motivation for standardization of NAND flash is to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased competition among manufacturers. ONFI has produced a specification Version 1.0 for a standard interface to NAND flash chips. The current specification includes a standard physical interface, NAND chip self-identification and self-description standards, timing requirements, standard command set (e.g., command numbers and addressing scheme) for reading, writing, and erasing NAND flash in addition to performance and data integrity improvements. Thus, in addition to accommodating various proprietary or legacy NAND flash implementations, an improved flash channel interface should be able to accommodate such ONFI standard based flash implementations.
In addition to design flexibility, as file and resultant flash device sizes continue to increase, maintaining or increasing read/write speeds while maintaining data integrity will become an increasingly crucial design challenge. For example, error-correcting codes (ECC) have been employed in NAND flash devices in order to cope with the charge loss/gain mechanism and resultant error. However, conventional error detection and correction techniques take a substantial amount of time to conduct in flash memory operations. Moreover as flash memory ages, the number of errors for which error correction is required can increase, further exacerbating the problem. Thus, significant data throughput increases are desired, which can be directed in part at improvements over conventional ECC techniques (e.g., schemes that read out the data from flash then perform ECC functions on the data).
The above-described deficiencies are merely intended to provide an overview of some of the problems encountered in flash channel interface designs and are not intended to be exhaustive. Other problems with the state of the art may become further apparent upon review of the description of the various non-limiting embodiments of the subject innovation that follows.